1. Field of the Invention
The present invention relates to high density memory devices based on phase change memory materials, like chalcogenides, and on other programmable resistance materials, and methods for manufacturing such devices.
2. Description of Related Art
Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in the active region of the cell. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched into either different solid phases or mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states.
The change from the amorphous to the crystalline state is generally a lower current operation, requiring a current that is sufficient to raise the phase change material to a level between a phase transition temperature and a melting temperature. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process, allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from a crystalline state to an amorphous state. The magnitude of the needed reset current can be reduced by reducing the volume of the active region in the phase change material element in the cell. Techniques used to reduce the volume of the active region include reducing the contact area between electrodes and the phase change material, so that higher current densities are achieved in the active volume, with small absolute current values through the phase change material element.
A memory cell structure under development, referred to sometimes as a “mushroom” cell because of the shape of the active region on the bottom electrode in a typical structure, is based on the formation of a small electrode in contact with a larger portion of phase change material, and then a usually larger electrode in contact with an opposite surface of the phase change material. Current flow from the small contact to the larger contact is used for reading, setting and resetting the memory cell. The small electrode concentrates the current density at the contact point, so that an active region in the phase change material is confined to a small volume near the contact point. See, for example, An et al., “Methods of Forming Phase Change Memory Devices having Bottom Electrodes,” United States Patent Application Publication No. US 2009/0017577; and Lung, “Method for Manufacturing a Small Pin on Integrated Circuits or Other Devices,” United States Patent Application Publication No. US 2006/0108667. Other structures of this type are described in U.S. Pat. No. 7,642,125 by Lung et al., and in references cited therein.
It has been proposed to make electrodes using sidewall spacers with trimmed widths, at least near the contact surface with the phase change material as shown in U.S. Pat. No. 6,617,192, by Lowrey et al. (See, FIG. 1D and column 9, lines 50-57). As shown in Lowrey et al., these sidewall spacer electrode have the thickness of the thin film sidewall material, resulting in a contact surface that is quite small, and which can be relatively uniform in size across an array. See also, Kim, et al., “High Performance PRAM Cell Scalable to sub-20 nm technology with below 4 F2 Cell Size, Extendable to DRAM Applications,” 2010 Symposium on VLSI Technology, Digest of Technical Papers, pages 203-204.
Also, it is desirable to provide a structure that can be laid out with a small number of lithographic steps or other patterning steps that require tolerance in the area of layout for alignment errors.
It is desirable therefore to provide a reliable electrode structure, and method for manufacturing a memory cell structure with control over the critical dimensions of the contact area between the electrode the memory material, which will work with high density integrated circuit memory devices.